Principal Network Systems Architect

The role

You will define scale-up and scale-out network architecture for Cerebras platforms. This includes proprietary accelerator interconnects, protocols, and switching.

What you will do

• Set the multi-generation architecture and roadmap for Cerebras scale-up networks and interfaces.
• Work with application, compiler, runtime, and communication-library teams to derive bandwidth, latency, ordering, availability, and serviceability.
• Define fabric topology, protocols, and switch behavior.
• Decide when to use standards-based technology or merchant silicon versus custom protocols or switches.
• Use performance models, traffic simulation, prototypes, and lab data to test architecture choices.
• Write architecture and interface specifications.
• Lead design reviews and drive cross-layer decisions through implementation, bring-up, and qualification.

Required qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Typically 12 or more years of relevant industry experience.
• Principal-level technical ownership of a major networking, switching, accelerator, or HPC system from architecture into implementation or deployment.
• Deep expertise in low-latency or proprietary interconnects, fabric protocols, switch architecture, or a closely related area.
• Experience deriving network requirements from incomplete workload and system information.
• Working knowledge of Ethernet, IP, and RDMA.
• Conceptual familiarity with BGP and EVPN.
• Architectural judgment grounded in prior implementation, modeling, silicon, lab, bring-up, or debugging work.
• A record of making clear technical decisions and influencing engineering leaders, implementation teams, suppliers, and customers.

Nice to have

• Proprietary accelerator interconnects or scale-up technologies such as NVLink, xGMI, TPU ICI, Xe Link, or UALink-class systems.
• Switch ASIC, NIC or DPU, accelerator I/O, transport offload, collective acceleration, coherent memory, or custom-fabric work.
• FPGA architecture or mapping experience, or work with other placement-sensitive systems where topology materially affects communication.
• AI or HPC communication stacks such as NCCL, RCCL, MPI, SHMEM, or proprietary collective libraries.
• RoCE, InfiniBand, PCIe, CXL, or other relevant scale-out and I/O technologies.
• Workload-driven modeling, traffic simulation, emulation, or pre-silicon and post-silicon correlation.
• Working awareness of SerDes, packaging, retimers, cabling, optics, and reach constraints.

Benefits

• Build a breakthrough AI platform beyond the constraints of the GPU.
• Publish and open source cutting-edge AI research.
• Work on one of the fastest AI supercomputers in the world.
• Job stability with startup vitality.
• Simple, non-corporate work culture that respects individual beliefs.

About the company

Cerebras Systems builds the world's largest AI chip. The company works with leading model labs, global enterprises, and cutting-edge AI-native startups.