Senior Product, Test and Yield Enhancement Engineer - Taiwan

The role

You will drive the test strategy for future generations of the Cerebras Wafer Scale Engine in Taiwan. This includes ATE test development, manufacturing-data analysis, wafer disposition, defect characterization, failure isolation and yield improvement for AI processors, high-speed I/O and memory.

What you will do

• Develop and optimize production test programs for wafer-scale AI processors.
• Drive high-volume manufacturing testing in partnership with foundries and OSATs.
• Implement and optimize design-for-test strategies including scan, BIST, ATPG and functional testing.
• Analyze ATE, Shmoo, parametric and defect data to improve yield and fault tolerance.
• Develop failure-analysis and fault-isolation methods for defective cores, tiles and other functional blocks.
• Build efficient wafer-level test flows for massively parallel compute, mesh and network-on-chip architectures, and die-to-die interconnects.
• Partner closely with DFT, architecture, design, performance, software and manufacturing teams.
• Optimize voltage-frequency operating limits, current, thermal behavior, power delivery and parallel die-testing capabilities.
• Support wafer and lot disposition decisions throughout high-volume manufacturing.

Required qualifications

• BS or MS in Electrical Engineering, Computer Engineering or a related field.
• 10+ years of semiconductor product or test-engineering experience supporting highly integrated devices.
• Strong experience in test development, silicon debug, test optimization and yield improvement.
• Experience testing large parallel processors, GPUs, CPUs or networking ASICs incorporating SRAM, DDR/DRAM or HBM.
• Expert-level, hands-on experience with the Advantest V93000 platform.
• Experience specifying, designing, developing and debugging load boards and probe cards for advanced production-test and DFT requirements.
• Strong cross-functional collaboration and problem-solving skills.
• Experience working with Git-based development and release flows.

Nice to have

• Teradyne experience is a plus.
• Programming experience with C, C++, Python or Perl for large-scale test-data analysis.
• Experience with semiconductor test and failure-analysis tools or techniques such as Tessent, OBIRCH, IREM and LADA.
• Experience testing high-speed SerDes at the ATE, package or system level.
• Experience with analog blocks embedded within large digital ASICs.
• Experience applying advanced data-analysis or machine-learning techniques to yield optimization.
• Knowledge of wafer-scale packaging, TSVs, advanced interconnects, in-line diagnostics and defect-mitigation techniques.

About the company

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. The company works with leading model labs, global enterprises, and cutting-edge AI-native startups.