STA/Timing Closure Lead

The role

The STA/Timing Closure Lead will develop solutions for closing timing on multi-billion instance ICs and 3D ICs. You will work with R&D to define product architecture and refine solutions at customer sites.

What you will do

• Design approach to timing closure for very large designs and 3D ICs with the R&D team.
• Run backend and timing flows with customers.
• Use customer learning to improve the product.
• Share customer feedback with research and product teams to help set priorities.
• Act as in house expert on STA and timing closure.

Required qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years running STA and timing closure at a tier 1 design houses.
• Experience closing timing at advanced process nodes.
• Strong hands on experience with commercial synthesis and timing tools such as Design Compiler and Fusion Compiler.
• Deep knowledge of STA, Liberty formats, and device characterization.
• Background in device physics at advanced nodes.
• Experience with die to die or chiplet to chiplet timing closure.
• Experience closing timing on 3D ICs, including TSV design and interconnect timing.
• Interest in working directly with customers and shaping the product.

Nice to have

• Experience with the broader implementation flow, including place and route.
• Experience using AI coding agents such as Claude Code, Codex, or OpenCode.
• Scripting experience in Python, Tcl, or Makefiles.

Benefits

• Unlimited PTO
• full benefits (medical, vision, dental, 401k)
• Two engineering-centric offices with free parking, private gym, and free lunch, drinks and snacks

About the company

ChipAgents is revolutionizing chip design and verification with agentic-AI workflows. They partner with top-10 semiconductor companies, hyperscale cloud providers, and cutting-edge startups.