Mixed-signal Verification Engineer

The role

You will own the methodology, planning, and execution of mixed-signal verification for digital-to-analog interfaces on Arago's Systems-on-Chip. You will work across analog, RTL, architecture, and firmware teams to ensure correct integration and drive verification to sign-off.

What you will do

• Own the mixed-signal verification methodology and verification plan for digital-to-analog interfaces on Arago SoCs.
• Build and maintain verification environments at block, subsystem, and SoC level.
• Develop tests, assertions, checkers, scoreboards, and functional coverage.
• Verify digital control and configuration of analog/mixed-signal circuitry across normal operation, corner cases, and error conditions.
• Run regressions, analyze coverage, debug failures, and drive verification to sign-off.
• Develop or integrate behavioral and real-number models needed for efficient mixed-signal simulation.
• Work closely with analog, RTL, architecture, firmware, and SoC verification teams to identify and resolve interface issues.

Required qualifications

• Strong hands-on experience in ASIC or SoC verification.
• Experience verifying mixed-signal blocks or digital-to-analog and analog-to-digital interfaces.
• Experience with AMS (analog-mixed-signal) co-simulation flow, and setting up mixed-signal testbenches.
• Strong SystemVerilog skills and practical experience with UVM or an equivalent verification methodology.
• Experience building verification environments and developing tests, assertions, scoreboards, and functional coverage.
• Good understanding of both digital design fundamentals and basic analog/mixed-signal concepts.
• Strong debugging skills, including the ability to investigate issues spanning RTL, models, clocks, resets, configuration, and analog behavior.
• Experience with scripting and automation, preferably Python, Tcl, shell, or similar.
• English at a proficient level.

Nice to have

• Verification experience with complex high-speed interface IP such as PCIe, DDR/LPDDR, UCIe, SerDes, USB, CXL, or similar PHY-based interfaces.
• Experience verifying interface initialization, link training, calibration, adaptation, clocking, power-state transitions, or other digital/analog control loops.
• Experience with real-number modeling, SystemVerilog RNM, wreal, Verilog-AMS, or equivalent mixed-signal verification techniques.
• Experience developing or integrating behavioral models of analog/PHY components into digital verification environments.
• Experience with SoC-level integration and verification of complex interface IP.
• Experience with low-power verification, power-state management, or UPF.
• Experience driving a complex IP or SoC verification effort through coverage closure and tape-out.

Benefits

• Competitive cash compensation
• Meaningful stock option plan
• Healthcare coverage (including family-friendly options)
• Pension contributions
• Professional development support
• 25 days of PTO
• Public holidays

About the company

Arago's mission is to re-engineer the foundations of computing from first principles. The company uses proprietary technology that fuses optical and CMOS technologies to deliver an order-of-magnitude increase in performance.