Staff Analog Design Engineer, SerDes Clocking

The role

This person will own the transistor-level analog design of the clocking subsystem for high-speed SerDes on an IO chiplet. The role involves designing PLL, DLL, phase interpolator, clock distribution, and CDR loops from specification through silicon characterization.

What you will do

• Own transistor-level design of low-jitter frequency synthesis including LC and/or ring PLL.
• Own the phase interpolator and phase rotation scheme.
• Design high-frequency clock distribution across the SerDes macro.
• Define and verify CDR architecture and loop dynamics.
• Model loop behavior in MATLAB, Python, or equivalent.
• Build phase-noise and jitter budgets for the link.
• Build the verification environment for blocks using PSS/HB, transient noise analysis, PVT corner coverage, and Monte Carlo.
• Provide behavioral and Verilog-A models for full-chip verification.
• Drive layout of blocks in deep sub-micron nodes.
• Take blocks through silicon bring-up and bench characterization.

Required qualifications

• BS/MS/PhD in Electrical Engineering
• 5+ years of hands-on analog and mixed-signal circuit design experience
• Demonstrated ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon in a high-speed SerDes link
• Deep knowledge of PLL architecture, loop dynamics, VCO design, and phase noise theory
• Working knowledge of CDR architectures and the loop analysis behind jitter tolerance and jitter transfer
• Practical experience with jitter decomposition and budgeting methodology
• Circuit design experience in advanced FinFET or GAA process nodes
• Experience using industry-standard analog design and simulation tools such as Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, and post-layout simulation
• Silicon bring-up and bench debug experience with lab equipment such as phase noise analyzers, high-speed scopes, and BERTs

Nice to have

• Die-to-die interconnect experience — UCIe, BoW, or a proprietary D2D PHY
• Forwarded-clock and matched-source-synchronous architectures alongside embedded-clock CDR
• Digital and hybrid PLL/CDR implementations, including the digital calibration around them
• Familiarity with relevant specifications: UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7
• Experience porting a clocking block across process nodes
• Participation in or contribution to standards bodies

About the company

d-Matrix has pioneered a memory-centric architecture that brings compute directly into memory to make AI faster and more energy efficient. The team works on chips, software, and rack-scale systems to tackle AI infrastructure challenges.