Sr. Staff PCB Design Engineer

The role

You will lead the physical design of boards that connect AI silicon to the world. You will own layout for high-complexity, high-layer-count PCBAs and drive design methodology, automation, and constraint management.

What you will do

• Lead full-cycle layout for high-complexity AI accelerator cards and system baseboards
• Architect and manage the Constraint Manager hierarchy in Cadence Allegro
• Develop automation scripts to streamline layout tasks, DRC checks, and reporting
• Execute layout for ultra-high-speed interfaces including PCIe Gen5/6, CXL, and custom die-to-die interconnects
• Partner with Power Engineers on PDN strategy
• Drive PCB stack-up definition
• Serve as primary interface with fabricators and CMs to ensure DFM, DFT, and DFA requirements are met

Required qualifications

• BS in Electrical/Electronic Engineering or equivalent practical experience
• 10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators
• Proficiency in Cadence Allegro Constraint Manager, including T-junctions, differential pair phase-tuning, and Z-axis delay matching
• Proven ability to write and deploy SKILL scripts or use Allegro's API to automate design audits and layout routines
• Deep understanding of high-speed routing techniques (back-drilling, via-in-pad, skip-vias) and HDI/ELIC design
• Proven track record routing 112G SerDes and complex DDR5/HBM interfaces

Nice to have

• Experience establishing a Library Management System and standardized footprint/padstack creation processes
• Familiarity with PLM/PDM integration for managing layout releases and ECO workflows
• Knowledge of PCB warpage mitigation strategies for large-form-factor ASICs and MCMs

About the company

d-Matrix has pioneered a memory-centric architecture that brings compute directly into memory. The team tackles AI infrastructure challenges by building chips, software, and rack-scale systems.