Sr. Staff Design Verification Engineer

The role

You will develop and execute verification plans across the SoC/IP verification cycle. You will build UVM/OVM-based environments and write SystemVerilog testbenches for complex ASIC/SoC designs.

What you will do

• Develop and execute verification plans across the SoC/IP verification cycle
• Build and maintain UVM/OVM-based verification environments
• Write and debug SystemVerilog testbenches
• Drive root-cause analysis and debug of verification failures
• Define and track coverage closure goals
• Partner cross-functionally with design, architecture, and physical design teams
• Contribute to the evolution of verification methodology and infrastructure

Required qualifications

• BS in Electrical Engineering, Computer Science, or a related field with 12+ years of industry experience
• Experience across the full SoC/IP verification cycle
• Hands-on ASIC/SoC design verification test development and debug experience
• Fluency with SystemVerilog (randomization, constraints, coverage, assertions)
• Fluency with verification methodologies such as UVM/OVM/VMM
• Strong problem-solving skills

Nice to have

• MS preferred with 7+ years
• Experience with C/C++ and SystemC
• Track record leading the creation and implementation of multiple SoC verification environments and driving tape-out efforts

About the company

d-Matrix has built a highly programmable in-memory computing architecture for AI inference. The company focuses on memory-centric architecture from chips to rack-scale systems.