D Matrix

Sr. Staff Power Performance Architect

Santa Clara, Remote. Posted 2 months ago

The role

The Senior Staff Power Performance Architect will own pre-silicon power estimation across next-generation AI accelerators. This person will build architectural power estimation tools and partner with front-end, DV, and backend teams to optimize power and performance.

What you will do

  • Own pre-silicon power estimation for design blocks at RTL and physical-design levels.
  • Partner with front-end and DV engineers to identify power activity windows and optimize power.
  • Build an architectural power estimation tool for AI workloads.
  • Collaborate with frontend architects and backend design to define performance monitor availability and system requirements.
  • Lead micro-architecture and RTL design, synthesis, and logic/physical power-performance verification.
  • Design and implement performance-enabling and power-saving/monitoring functions.
  • Participate in silicon bring-up and validation.

Required qualifications

  • 8+ years of relevant experience in IC power/performance architecture, RTL, or physical design
  • Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
  • Solid understanding of power, performance, micro-architecture, RTL, and physical design in the context of digital system and IC design
  • Familiarity with at least one EDA tool for power estimation
  • Ability to move fluidly between RTL, physical design, and automation
  • Programming proficiency in TCL and Python
  • Experience using libraries, APIs, data parsing, and algorithmic thinking

Nice to have

  • Exposure to power estimation and performance metrics such as TDP, PMAX, EDP, Peak, and Average
  • Familiarity with power/frequency scaling techniques (DFS, DVFS, AFS, AVFS)
  • Familiarity with power delivery network (PDN) analysis, including resonance, impedance (Z(f)), and voltage droop analysis

About the company

d-Matrix has pioneered a memory-centric architecture that brings compute directly into memory for AI inference. The team works on chips, software, and rack-scale systems to tackle AI infrastructure challenges.