Staff Analog Design Engineer, TX/RX Datapath

The role

You will own the transmit and receive datapath of the high-speed SerDes on an IO chiplet. This role involves transistor-level design from specification through silicon characterization.

What you will do

• Own transistor-level design of the SerDes transmit path including output drivers, pre-driver, serializer stages, and transmit-side FFE
• Own transistor-level design of the receive front-end including termination, ESD-aware input network, CTLE, VGA, samplers, and ADC-based front-ends
• Design and verify the equalization path and own the architecture trade study
• Derive block-level specifications from link budgets and defend them in design review
• Build the verification environment including testbenches, PVT corner coverage, and Monte Carlo simulations
• Provide behavioral and Verilog-A models for full-chip verification
• Perform link and channel modeling in MATLAB, Python, or equivalent
• Drive layout of blocks in deep sub-micron nodes and co-design with package/signal-integrity engineers
• Contribute to testboard design and take blocks through silicon bring-up and bench characterization

Required qualifications

• BS/MS/PhD in Electrical Engineering
• 8+ years of hands-on analog and mixed-signal circuit design experience
• Demonstrated ownership of a SerDes transmit or receive datapath block through to working silicon in a high-speed link
• Deep knowledge of high-speed driver design, receive front-end design, and equalization
• Practical familiarity with adjacent clocking and CDR blocks
• Practical command of jitter and noise analysis
• Circuit design experience in advanced FinFET or GAA process nodes
• Hands-on use of industry-standard analog design and simulation tools (e.g., Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, post-layout simulation)
• Link/channel modeling experience (e.g., MATLAB, Python, S-parameter models)
• Silicon bring-up and bench debug experience with high-speed lab equipment such as scopes and BERTs

Nice to have

• Die-to-die interconnect experience — UCIe, BoW, or a proprietary D2D PHY
• PAM4 signaling and DSP-based receiver architectures, including ADC-based front-ends
• Familiarity with relevant specifications: UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7
• Experience porting a datapath block across process nodes
• IBIS-AMI model generation, or SerDes ATE and production test development
• Participation in or contribution to standards bodies

About the company

d-Matrix has pioneered a memory-centric architecture that brings compute directly into memory. The team builds chips, software, and rack-scale systems to tackle AI infrastructure challenges.