Physical Design Engineer - Full Chip Implementation

The role

You will own full-chip implementation from synthesis through to GDSII completion. This includes floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs.

What you will do

• Own full-chip clocking across all PVT corners and modes.
• Manage MMMC timing closure at the top level.
• Own timing constraints and hierarchical timing budgeting between top level and blocks.
• Drive functional and timing ECO closure and achieve final timing signoff for tapeout.
• Own end-to-end physical verification closure at block, sub-system, and full-chip level.
• Debug complex PV violations and fix violations directly in layout using Innovus.
• Build a repeatable, tapeout-ready PV methodology.

Required qualifications

• 10+ years of previous experience with chip planning, top level PD, floorplanning
• Experience with top-level and full-chip closure on advanced process nodes (5nm and below)
• Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows
• Experience with Synopsys PrimeTime and Cadence Tempus for timing signoff
• Experience with Pegasus or Calibre for physical verification signoff
• Experience with hierarchical timing budgeting, constraint management, and ECO closure
• Experience with Cadence Innovus for top-level assembly, routing, and layout fixes
• Deeply creative and able to think from first principles

Nice to have

• Familiarity with modern ML and LLM model architectures
• Ability to program with Python or another scripting language
• Familiarity with AI tools for programming/coding
• Startup experience or comfort working in fast-paced environments

Benefits

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2.5k per month for those living within walking distance of the office
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch and dinner in our office
• Unlimited compute budget subject to ROI justification

About the company

Etched is building hardware for frontier intelligence by co-designing chips, racks, software, and manufacturing. They are a fully in-person team in San Jose (Santana Row).