Formal Verification - DV

The role

A Formal Verification Engineer will drive formal verification across custom IP, interface IP, and SoC subsystems. You will work with architects, designers, and software teams to prove design correctness and improve verification closure.

What you will do

• Define and drive formal verification strategy across the ASIC DV team.
• Develop formal verification plans covering functional correctness, connectivity, and deadlock/livelock freedom.
• Build reusable formal environments using SystemVerilog Assertions, assumptions, constraints, and models.
• Drive proof convergence using abstractions, cut-points, and coverage metrics.
• Translate design intent and specifications into formal properties and closure criteria.
• Partner with UVM DV, emulation, software, and firmware teams.
• Debug complex RTL, protocol, datapath, connectivity, and integration bugs.
• Contribute to formal sign-off methodology, regression automation, and design-for-formal best practices.

Required qualifications

• 5+ years of design verification experience, including significant hands-on formal verification experience on complex digital designs or shipping silicon.
• Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology.
• Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal.
• Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces.
• Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models.
• Strong debugging skills across RTL, specifications, formal counterexamples, simulation waveforms, and verification reports.
• Experience collaborating across architecture, RTL design, UVM DV, emulation, software, firmware, and vendor teams.
• Ability to thrive in a fast-paced startup environment and take ownership of ambiguous, high-impact verification problems.

Nice to have

• Formal verification of systolic arrays, DMA engines, NoCs, memory subsystems, arithmetic datapaths, PCIe, Ethernet, AXI/AMBA, CPU interfaces, or low-power controllers.
• Protocol compliance checking, connectivity checking, register verification, datapath validation, reset verification, or deadlock/livelock analysis.
• Vendor IP integration, encrypted or black-box IP verification, VIP configuration, or contract-based verification.
• Sequential LEC, floating-point or integer arithmetic proofs, cache coherency checks, interrupt handling, or memory-mapped IO verification.
• Scripting in Python, TCL, Perl, or similar for automation, regression management, debug, and dashboarding.

Benefits

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2.5k per month for those living within walking distance of the office
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch + dinner in our office

About the company

Etched is building hardware for frontier intelligence by co-designing chips, racks, software, and manufacturing. They are a fully in-person team in San Jose (Santana Row).