DFT Intern

The role

You will review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams and contribute to DFT verification and ATPG fault model flows.

What you will do

• Review and refine DFT flow automation to support chip-level regression on Caelius
• Work across frontend and backend design teams
• Contribute to DFT verification including MBIST, Scan, BSCAN, and SSN simulations
• Develop flows for various ATPG fault models

Required qualifications

• Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field
• Familiarity with a hardware description language (Verilog or SystemVerilog)
• Exposure to ASIC or SoC design concepts
• Familiarity with digital logic design fundamentals
• Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)
• Familiarity with scripting in Python, Tcl, or another language
• Able to learn quickly about transformers and other aspects of modern artificial intelligence

Nice to have

• Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression
• Experience with Tessent or similar DFT tooling
• Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)
• Exposure to DFT flow automation or regression infrastructure
• Familiarity with clocking and reset schemes

Benefits

• Paid internship
• Generous housing support for those relocating
• Daily lunch and dinner in our office
• Direct mentorship from industry leaders and world-class engineers

About the company

Etched is building hardware for frontier intelligence by co-designing chips, racks, software, and manufacturing. They are a fully in-person team in San Jose.