Design Verification Engineer - Interface IP

The role

You will work with architects, designers, and vendors to ensure architecture requirements are met in IP subsystems and interfaces. You will validate correctness and performance across the full hardware-software stack.

What you will do

• End to end ownership of IP subsystems including PCIe, Ethernet, CPU (arc/arm), low power peripherals, or sensors
• Understand vendor IP configurations and handle handshake with internal IP team
• Develop and maintain UVM/SystemVerilog-based verification environments
• Collaborate with integration and SoC DV teams to validate interaction of external IPs
• Drive coverage closure and sign-off by defining metrics and analyzing gaps

Required qualifications

• 5+ years of design verification experience
• Hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM
• Understand how to build scalable, reusable testbenches
• Comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs

Nice to have

• Experience handling vendors and integration of IP/VIP’s
• UVM/System Verilog

Benefits

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch + dinner in our office
• Unlimited compute budget subject to ROI justification

About the company

Etched is building hardware for frontier intelligence by co-designing chips, racks, software, and manufacturing. The company is an inference-focused frontier AI system.