RTL Design Engineer

The role

You will develop and implement design verification strategies for existing and upcoming ASIC designs. You will work with state-of-the-art architectures for machine learning.

What you will do

• Develop and implement design verification strategies for existing and upcoming ASIC designs
• Implement a block to efficiently compute floating point math operators
• Provide feedback to the uArch team to make sure blocks meet timing and area constraints

Required qualifications

• At least 5 years of work experience in RTL development
• Experience with high-speed digital logic
• Proficiency in standard RTL design and synthesis tools
• Familiarity with verification work and writing test benches
• Able to learn quickly about transformers and other aspects of modern artificial intelligence
• Willing to start quickly

Nice to have

• Experience with PCIe, Ethernet, or HBM technologies
• Familiarity with modern ML and LLM model architectures
• Familiarity with numerical representations and functions
• Ability to program with Python or another scripting language

Benefits

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2.5k per month for those living within walking distance of the office
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch + dinner in our office
• Unlimited compute budget subject to ROI justification

About the company

Etched is building hardware for frontier intelligence by co-designing chips, racks, software, and manufacturing. The company is a fully in-person team in San Jose (Santana Row).