DFT (Design For Test) Engineer

The role

The DFT Engineer will develop and implement DFT architectures for ASIC and SoC designs. This role involves integrating DFT methodologies, collaborating with design teams, and supporting silicon bring-up and production.

What you will do

• Develop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs.
• Integrate industry-standard DFT methodologies such as scan insertion, boundary scan, BIST, and MBIST.
• Collaborate cross-functionally with design and verification teams.
• Analyze test results and silicon debug data to provide design feedback.
• Create and execute comprehensive DFT verification plans.
• Apply simulation-based and formal verification techniques.
• Conduct internal DFT audits and design reviews.
• Support silicon bring-up, debug, and failure analysis during post-silicon validation.
• Partner with test engineering teams to develop and optimize ATE programs.
• Generate production-quality test patterns.

Required qualifications

• 10+ years of experience in DFT engineering with a track record of successful test implementations for ASIC or SoC products.
• Deep understanding of digital design, verification methodologies, and DFT implementation practices.
• Proficiency in System Verilog.
• Fluency with industry-standard EDA tools (e.g., Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent).
• Scripting and automation experience using Python, Perl, or TCL.
• Track record of leading DFT initiatives across multiple product generations in high-performance or high-volume silicon environments.
• Strong analytical and debugging skills.
• Excellent communication and collaboration abilities.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.

Nice to have

• Master’s degree
• Mixed-signal DFT methodologies and integration of analog testability into SoC workflows
• Industry standards such as IEEE 1149.1 (JTAG), IEEE 1500, and experience applying them in complex designs
• Yield analysis, product engineering, and contributions to test cost reduction and quality improvement programs

Benefits

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2.5k per month for those living within walking distance of the office
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch + dinner in our office
• Unlimited compute budget subject to ROI justification

About the company

Etched is building hardware for frontier intelligence by co-designing chips, racks, software, and manufacturing. They are a fully in-person team in San Jose (Santana Row).