DV Intern

The role

As a Design Verification intern, you will ensure custom IPs including systolic arrays, DMA engines, and NoCs are robust, high-performance, and silicon-ready. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.

What you will do

• Ensure custom IPs powering chips are robust, high-performance, and silicon-ready
• Collaborate with architects, RTL designers, and SW/FW/emulation teams
• Validate correctness and performance across the full hardware-software stack

Required qualifications

• Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field
• Familiarity with high-speed digital logic
• Exposure to ASIC or SoC design concepts
• Familiarity with SystemVerilog, UVM, or Python
• Familiarity with verification work and writing test benches
• Familiarity with physical design flows and tooling
• Able to learn quickly about transformers and other aspects of modern artificial intelligence

Nice to have

• Familiarity with modern ML and LLM model architectures
• UVM or formal verification experience
• Ability to program with Python or another scripting language

Benefits

• Generous housing support for those relocating
• Daily lunch and dinner in our office
• Direct mentorship from industry leaders and world-class engineers

About the company

Etched is building hardware for frontier intelligence by co-designing chips, racks, software, and manufacturing. The company is a fully in-person team in San Jose focused on inference.