Etched
Physical Design Engineer
Austin. Posted 7 months ago
The role
Physical Design engineers will own block-level implementation and verification. You will drive timing closure and PPA optimization, supervise 3rd party design work, and help improve design flows and iteration speed.
What you will do
- Running PD flows to close blocks
- Support ASIC infrastructure
- Automate PD flows
- Improve CAD infrastructure
- Collaborate with RTL Designers to improve PPA
- Drive dashboards that show the convergence of projects related to PD
- Optimize tool flows with EDA vendors
- Accountable for block level closure
- Supervise the outsourcing of physical design to a 3rd party service
Required qualifications
- 5-10+ years of previous experience with PD
- Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
- Experience with back-end design and timing closure on advanced process nodes (5nm and below)
- Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows
- Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
- Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysi
- Deeply creative and able to think from first principles
Nice to have
- Familiarity with modern ML and LLM model architectures
- Ability to program with Python or another scripting language
- Familiarity with AI tools for programming/coding
- Startup experience or comfort working in fast-paced environments
Benefits
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch + dinner in our office
- Unlimited compute budget subject to ROI justification
About the company
Etched is building hardware for frontier intelligence. They co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads.