Senior/Staff Design for Test Engineer

The role

This person will architect, own, and implement DFT strategies for complex high-throughput digital pipelines in advanced CMOS nodes. They will lead the integration and verification of DFT features and partner with test engineering teams to optimize test patterns.

What you will do

• Architect, own, and implement the comprehensive Design-for-Test (DFT) strategy for complex high-throughput digital pipelines in advanced CMOS nodes.
• Lead the integration and verification of all DFT features, including Scan, JTAG, Boundary Scan, and Memory BIST.
• Partner with the test engineering team to develop, validate, and optimize ATE-compatible test patterns.
• Drive RTL development with a focus on DFT architecture.
• Collaborate on formal and constrained-random verification of DFT logic.
• Analyse and minimise the DFT impact on power, performance, and area (PPA).
• Collaborate with mixed-signal and software teams to define and optimise DFT interfaces, test modes, and firmware abstractions.
• Mentor junior engineers, lead DFT design reviews, and champion best-practice methodologies.

Required qualifications

• 7+ years of hands‑on DFT architecture, implementation, and verification for high‑performance ASICs or SoCs.
• Ownership of at least one product with comprehensive DFT coverage.
• Proven success implementing and verifying advanced DFT features on multi‑hundred‑MHz to multi‑GHz clock domains.
• Expertise with industry‑standard EDA flows: Scan insertion, ATPG, pattern simulation (gate-level), fault modeling, and diagnosis tools.
• Demonstrated proficiency with DFT flows: compression techniques, EDT, JTAG/IEEE 1149.1/1687, and managing large pattern sets.
• Proficiency using Python/Tcl scripting for DFT flow automation, pattern generation/management, and silicon debug/bring-up.
• Solid grounding in semiconductor device physics, fault models (stuck-at, transition, bridging), and yield enhancement strategies.
• Excellent communication and cross‑functional collaboration abilities.

Nice to have

• Tape‑out experience at 22 nm or below.
• Knowledge of high-speed SerDes or HBM/DDR DFT challenges.
• Familiarity with AI/ML workloads or systolic arrays and their implications for DFT.
• Contributions to open‑source DFT tools or verification frameworks.

Benefits

• Competitive Salary
• Meaningful stock options
• Annual Living-Local Bonus if your residence is within 20 minutes of the office
• Employer-contributed retirement plans

Before you apply

• Candidates eligibility to work at OLIX depends on their most recent citizenship or permanent residency status.
• Generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, Ch

About the company

OLIX is creating the OLIX Decode Accelerator 1 (DX-1), the first accelerator architected specifically for decode. The company aims to address the infrastructure gap in AI by providing a new paradigm for hardware.