Digital Design Verification Engineer

The role

Senior / Staff Digital Verification Engineers will take ownership of the functional correctness of high-speed, real-time data-processing silicon. This includes work from early algorithm modelling through verified RTL, sign-off, and silicon bring-up.

What you will do

• Own end-to-end verification of high-throughput digital pipelines
• Develop and maintain verification environments using SystemVerilog/UVM
• Define and implement assertion-based verification strategies
• Apply formal verification techniques
• Model and validate algorithms using MATLAB/Simulink or Python
• Support FPGA prototyping and silicon bring-up
• Collaborate with digital design, optical-hardware, mixed-signal, and software teams
• Analyse verification results to identify root causes
• Contribute to verification methodology development, documentation, and reviews
• Mentor junior engineers where appropriate

Required qualifications

• 5+ years of hands-on experience in digital verification for high-performance ASICs or SoCs
• Ownership of verification for at least one complex block or subsystem processing continuous real-time data streams
• Strong proficiency in SystemVerilog, assertions (SVA), and modern verification methodologies (e.g. UVM. CocoTB)
• Proven experience verifying designs operating in GHz-class clock domains, including CDC/RDC analysis
• Familiarity with industry-standard EDA flows: RTL simulation, formal verification, linting, CDC/RDC, STA, power-intent (UPF/CPF), and gate-level simulation
• Experience verifying high-speed IP such as SerDes, DDR/HBM, PCIe, Ethernet, or similar interfaces
• Proficiency with MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed-point analysis, and test-vector generation
• Solid grounding in digital design principles, computer architecture, DSP fundamentals, and semiconductor basics
• Clear communicator who collaborates effectively across disciplines

Nice to have

• Tape-out experience on an advanced process node
• Deep hands-on experience with formal verification methodologies, including property decomposition, and coverage-driven formal on tools such as Jasper
• Exposure to coherent optical links or photonic-electronic co-design
• Familiarity with AI/ML workloads, systolic arrays, or tensor-processing architectures
• Expertise in arithmetic pipeline verification
• Expertise in processor and ISA verification
• Contributions to open-source RTL, verification frameworks, or FPGA platforms

Benefits

• Competitive Salary
• Meaningful stock options
• Annual Living-Local Bonus if your residence is within 20 minutes of the office
• Employer-contributed retirement plans

Before you apply

• Candidates eligibility to work at OLIX depends on their most recent citizenship or permanent residency status
• Generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, Ch

About the company

OLIX is creating the OLIX Decode Accelerator 1 (DX-1), the first accelerator architected specifically for decode. The company aims to address the massive infrastructure gap in AI through rack-scale co-design of logic, data movement, packaging, optics and interconnect.