Senior Compiler Engineer

London, UK. Posted 19 days ago

The role

You will build the ML backend including the compiler, run-time, and debugger for next-generation hardware. You will connect PyTorch, Tensorflow, JAX, and MXNet to low-level kernel drivers.

What you will do

Own and deliver projects on the team roadmap.
Design and implement the compiler, runtime, and debugger for PyTorch, TensorFlow, JAX, and MXNet on custom hardware.
Apply advanced techniques like layout, fusion, scheduling, and tiling to maximize throughput.
Lead code reviews, coach peers, and uphold best practices.
Stay ahead of GPU and AI accelerator trends to propose and prototype innovations.

Required qualifications

5+ years of experience in software engineering with a focus on C/C++ programming.
Deep expertise in ML framework internals, compilers, low-level programming, and optimisation techniques.
Deep expertise in optimising Tensorflow, PyTorch or JAX deep learning models.
Deep expertise with multiple toolchains like LLVM, OpenXLA/XLA, MLIR, TVM.
Practical experience applying machine learning in high-performance computing contexts.
Strong problem-solving skills and the ability to think critically and creatively.
Experience in high-pace, dynamic work environments.
Excellent teamwork and communication skills.
Bachelor's degree in computer science, electrical engineering, telecoms engineering, mathematics, or a related field.

Nice to have

Personal projects

Benefits

Meaningful stock options
Annual Living-Local Bonus if your residence is within 20 minutes of the office
Employer-contributed retirement plans

Before you apply

Candidates eligibility to work at OLIX depends on most recent citizenship or permanent residency status due to U.S. export control regulations.
Generally unable to consider applicants whose most recent citizenship or permanent residence is in Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela.

About the company

OLIX is building the OLIX Decode Accelerator 1 (DX-1), the first accelerator architected specifically for decode. The company aims to address the infrastructure gap in AI through rack-scale co-design of logic, data movement, packaging, optics and interconnect.