Design Verification Engineer

The role

You will verify complex hardware systems including IP blocks, subsystems, and full SoC. You will work with architecture, RTL, software, and systems teams to ensure functional correctness for ML accelerators.

What you will do

• Own the verification of custom IP blocks, subsystems, or full-chip SoC-level functionality.
• Define verification plans based on architecture and microarchitecture specs.
• Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.
• Build and maintain stimulus generators, checkers, monitors, and scoreboards.
• Drive bug triage and root cause analysis.
• Work closely with design teams on resolution.
• Contribute to regression infrastructure, coverage analysis, and closure.

Required qualifications

• BS/MS in EE/CE/CS or equivalent
• 3+ years of experience in hardware verification
• Proven success verifying complex IP or SoC designs in industry-standard flows
• Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi)
• Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives
• Experience working in fast-paced, cross-disciplinary teams

Nice to have

• Familiarity with performance modeling, formal verification, or emulation

Before you apply

• Candidates may need to meet certain legal status requirements to comply with U.S. export control laws and regulations.
• Background checks for applicants will be administered in accordance with applicable law.

About the company

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. The Hardware organization develops AI-native silicon and system-level solutions.