RTL Lead

The role

You will lead and own the design of digital logic for thermodynamic hardware. This includes writing microarchitecture specifications, creating synthesizable SystemVerilog, and working from microarchitecture to tapeout.

What you will do

• Organize and set the standard and high expectations for the RTL design team
• Create and enforce RTL coding standards
• Write and own synthesizable RTL in SystemVerilog
• Translate high-level specifications into implementable microarchitectures
• Work with the verification team to review plans and assist on debug
• Collaborate with physical design on timing closure, PPA optimization, floorplanning constraints, and DFT
• Participate in design reviews and contribute to architecture decisions
• Support tapeout preparation and signoff on tapeout readiness
• Support post-silicon bring-up as needed

Required qualifications

• Experience leading an RTL design team through multiple tapeouts including block and toplevel work
• Hands-on experience writing production RTL in SystemVerilog
• Experience closing RTL through synthesis and place-and-route for multiple blocks and design
• Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront
• Strong debugging instincts across simulation, waveforms, and formal counterexamples
• Ability to work directly with architects and physical designers

Nice to have

• Experience at an AI chip company where design and verification were tightly coupled
• Experience with multiple interface architectures, for example PCIe, Ethernet, and memory devices
• Familiarity with FPGAs
• Experience with AI-assisted RTL or EDA tooling in your design workflow
• Exposure to physical design constraints, floorplanning, or timing-driven RTL development

About the company

Normal is an applied AI company solving problems in AI and silicon. They build foundational hardware and software for the semiconductor industry and critical AI infrastructure.