Hardware Engineer, Performance Modeling

The role

You will build the transaction-level model of physics-inspired ASICs. You will own the path from RTL to numerical performance results by correlating the TLM against RTL, FPGA prototypes, and synthesis results.

What you will do

• Build and maintain a cycle-accurate approximate TLM of compute tiles, memory hierarchy, and interconnect in SystemC, C++ or Python
• Translate TLM and RTL results into calibrated parameters to enable end-to-end system level performance prediction
• Provide the TLM as a reference golden model for DV, including transaction level scoreboards and performance checks
• Work with the DV and RTL team to ensure RTL produces the desired end-target behavior
• Plan modeling work against the hardware roadmap
• Run sensitivity studies on key hardware parameters to provide recommendations to architecture and hardware teams

Required qualifications

• 5+ years of experience in performance modeling at a major semiconductor company
• Demonstrated proficiency in understanding architectures and transforming that to performant modeling code
• Use of various modeling techniques and languages
• Excellent written and spoken communication skills

Nice to have

• Experience with AI acceleration hardware
• Experience with architecture-level modeling and cost tools such as AccelForge, Timeloop/Accelergy, CACTI, McPAT, or gem5
• Experience with DV methodology
• Hands-on use of LLMs or agentic tools in development workflows
• Exposure to analog, mixed-signal, or unconventional compute
• Experience with memory interfaces (LPDDR, HBM, DDR) and other I/O

About the company

Normal is an applied AI company solving the hardest problems in AI and silicon. They build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world.