Member of Technical Staff, ASIC Design

The role

You will perform RTL design of IPs, subsystems and SOCs for the silicon roadmap. You will provide technical leadership in microarchitecture specifications and design methodologies while collaborating with partner teams.

What you will do

• Responsible for RTL design of IPs, subsystems and SOCs supporting Netpreme's silicon roadmap.
• Provide technical leadership in defining IP/SOC microarchitecture specifications and design methodologies.
• Conduct design reviews to ensure adherence to best practices.
• Guide the team in optimizing the design to meet performance, power and area goals.
• Drive collaboration with architecture, verification, physical design, firmware, DFT, and post silicon domains.
• Interface with external IP vendors, foundries and EDA tool providers.

Required qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 5+ years of ASIC/SOC digital design experience
• Excellent leadership, communication, team building and stakeholder management skills.
• Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
• Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies.
• Outstanding technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies.
• Hands-on design experience in one or more industry standards/protocol stacks such as Ethernet, UCIe, UALink etc.
• Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).
• Proficiency with front-end development tools/methodologies, and scripting for automation and flow integration.

Nice to have

• Design and tapeout of any advanced silicon device is highly preferred.
• PhD in Electrical Engineering, Computer Engineering, or a related field.
• Experience managing relationships with external design partners, IP vendors, and foundries.
• Knowledge of Design-For-Testability, post silicon debug/validation/manufacturing test.

Benefits

• Competitive salary with performance-based bonus and early-stage equity grant
• 100% employer-paid Health, Dental, and Vision coverage for you and your dependents
• 401(k) match with immediate vesting
• Access to financial advisors
• 100% employer-paid Life, Disability, and AD&D insurance
• Fitness stipend
• Wellness & mental health perks
• 20 vacation days
• 15 company holidays (including 3 floating days)
• Daily lunch stipend
• Enterprise-level Claude & ChatGPT access
• On-site parking and EV charging

About the company

Netpreme is building a solution to the memory wall in AI systems through a proprietary memory management framework and X-Mem™ Memory Processing Unit silicon. Founded by MIT researchers, the company is based in Cambridge, MA, and Santa Clara, CA.