Phinitylabs
Physical Design Lead
San Francisco. Posted a month ago
The role
You will lead PD flows and optimization from block-level to full-chip level. You will define synthesis to layout flows and deliver tapeout ready designs using in-house prompt-to-GDS capability.
What you will do
- Leading PD flows and optimization of block-level to full-chip level optimizations
- Define Synthesis to layout flows, including PDN, clock-trees, PVT corners and custom cell definitions
- Implementing characterization flows for custom cells and memory blocks
- Executing IP and Fullchip design optimizations working with PD engineers
- Identify areas of optimization in design utilization, power grid and clock network within the design
- Delivering tapeout ready design optimized for the target PPA, and utilizing the in-house capability on prompt-to-GDS
Benefits
- Health insurance
- Retirement plans
- Unlimited PTO
- Paid parental leave
- Lunch and dinner provided in-office
About the company
Phinity is an AI research lab focused on solving chip design. The team builds RL environments, agent infrastructure, and evaluation systems to enable AI agents to tape-out chips autonomously.