Synthesis & Static Timing Analysis (STA) Engineer

The role

You will own the path from RTL to a timing-clean netlist. You will close timing on real silicon programs and help Voltai's AI learn to write constraints, diagnose violations, and close timing.

What you will do

• Own logic synthesis and constraint development (SDC) for blocks and full chips.
• Drive timing closure across corners and modes, working with RTL and physical design teams.
• Run and sign off STA, including on-chip variation, crosstalk, and multi-corner multi-mode analysis.
• Perform logic equivalence checking between RTL and netlist.
• Build automation that makes synthesis and timing flows faster and more reliable.
• Evaluate AI-generated constraints and timing fixes, and help define what good looks like.

Required qualifications

• 5+ years of synthesis and STA experience on production tapeouts.
• Deep experience with Design Compiler/Fusion Compiler or Genus, and PrimeTime or Tempus.
• Strong SDC skills: clocks, exceptions, generated clocks, and multi-mode constraints.
• Experience with logic equivalence checking (Formality or Conformal).
• Strong Tcl and Python scripting.

Nice to have

• Advanced node experience (7nm and below).
• Experience with ECO flows and timing signoff methodology.
• Interest in AI-assisted design tools.

About the company

Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. They are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.