Low-Power Design Engineer

The role

You will own power intent from architecture through signoff. You will design and verify low-power architectures on real silicon programs and help Voltai's AI learn power-aware design.

What you will do

• Define power architecture and write UPF power intent for SoCs and IP.
• Implement and verify power gating, clock gating, multi-voltage domains, and retention.
• Run power-aware simulation, static low-power checks, and CDC/RDC analysis.
• Partner with RTL, physical design, and signoff teams on power estimation and closure.
• Build automation for power analysis and reporting.
• Evaluate AI-generated power intent and help define what correct looks like.

Required qualifications

• 5+ years of low-power design or verification experience on production tapeouts.
• Expert UPF knowledge and experience with power-aware verification.
• Hands-on experience with tools like VC LP, Conformal Low Power, or PowerArtist.
• Experience with CDC/RDC tools (SpyGlass, Questa CDC, or similar).
• Python or Tcl scripting.

Nice to have

• Experience with mobile, edge, or data-center power management.
• Formal verification of power intent.
• Interest in AI-assisted design tools.

About the company

Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. They are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.