RTL Design Engineer

The role

You will design and own RTL for production silicon from microarchitecture to signoff-ready code. You will work on chip programs and help Voltai's AI learn to write, review, and debug RTL.

What you will do

• Own microarchitecture and RTL implementation for IP blocks and subsystems in SystemVerilog
• Drive designs through lint, CDC/RDC, synthesis, and timing closure with the backend team
• Partner with verification and formal teams on test plans, assertions, and coverage closure
• Debug complex functional and timing issues across simulation, emulation, and silicon
• Review and evaluate AI-generated RTL
• Help define what correct, high-quality design looks like
• Work directly with customer design teams when needed

Required qualifications

• 5+ years of RTL design experience on chips that taped out
• Expert SystemVerilog/Verilog and strong microarchitecture skills
• Hands-on experience with lint, CDC, synthesis, and timing-aware design
• Familiarity with common protocols (AXI, PCIe, Ethernet, DDR, or similar)
• Python or Tcl scripting

Nice to have

• Experience writing SVA or working with formal verification
• Low-power design (UPF, clock and power gating)
• Interest in AI-assisted design tools

About the company

Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. They are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.