Design for Test (DFT) Engineer

The role

You will define DFT architecture for SoCs and IP and own DFT architecture and implementation on real silicon programs. You will also help Voltai's AI learn DFT methodology.

What you will do

• Define DFT architecture for SoCs and IP, including scan, compression, MBIST, LBIST, and boundary scan.
• Insert and verify DFT logic, and generate ATPG patterns that meet coverage targets.
• Work with RTL, synthesis, and physical design teams to close DFT timing and area impact.
• Support silicon bring-up, pattern debug, and yield analysis with test and product engineering.
• Build automation for DFT flows and coverage reporting.
• Help define how AI can accelerate DFT insertion and pattern generation.

Required qualifications

• 5+ years of DFT experience on production tapeouts.
• Hands-on experience with Tessent, TestMAX, or Modus.
• Strong knowledge of scan, compression, ATPG, MBIST, and IEEE 1149.1/1687.
• Experience with DFT verification and gate-level simulation.
• Tcl and Python scripting.

Nice to have

• Post-silicon test bring-up and ATE experience.
• Experience with 2.5D/3D or chiplet test strategies.
• Interest in AI-assisted design tools.

About the company

Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. They are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.