Physical Design Engineer - STA

The role

You will drive static timing analysis and closure for complex, high-performance designs. You will collaborate with logic, DFT, and physical design teams to debug constraints, optimize paths, and ensure chips meet performance targets.

What you will do

• Drive static timing analysis and closure for complex, high-performance designs
• Collaborate with logic, DFT, and physical design teams
• Debug constraints, optimize paths, and ensure chips meet performance targets across corners and modes

Required qualifications

• 7+ years of industry experience
• Proven record of successful tapeouts
• Deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis
• Proficiency in writing and debugging SDC constraints, creating ECOs, and developing closure strategies
• Strong scripting skills in Python, Perl, and TCL
• Familiarity with SPICE modeling and worst-case corner analysis

Benefits

• Highly competitive compensation package and benefits

Before you apply

• Offer is contingent upon being eligible to access U.S. export-controlled technology
• Offer may be contingent upon citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency

About the company

Tenstorrent is leading the industry on cutting-edge AI technology. Their team has developed a high performance RISC-V CPU from scratch.