Physical Design Engineer, AI Accelerator IP

The role

This person will own the physical implementation of IP blocks end to end from synthesis through PnR, timing closure, and GDSII signoff. The role involves working with RTL owners to close critical paths and hit power budgets.

What you will do

• Own physical implementation of IP blocks end to end
• Perform synthesis through PnR, timing closure, and GDSII signoff
• Work closely with RTL owners to close critical paths and hit power budgets
• Build floorplans, power grids, pin placement, and clocking strategies
• Deliver IP integration collateral including LEF/DEF, timing and power models, GDS, and signoff reports

Required qualifications

• BS/MS/PhD in EE/ECE/CE/CS
• 5+ years of block-level or IP-centric physical design through tapeout
• Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime)
• Expertise with scripting languages (Tcl, Python, Perl)
• Deep understanding of advanced node challenges
• Deep understanding of low-power design (UPF, power gating, multi-Vt, voltage scaling)
• Deep understanding of signoff (STA, LEC)
• Experience building floorplans, power grids, pin placement, and clocking strategies
• Experience delivering IP integration collateral (LEF/DEF, timing and power models, GDS, signoff reports)

Benefits

• Highly competitive compensation package and benefits

Before you apply

• Offer is contingent upon being eligible to access U.S. export-controlled technology
• Offer may be contingent upon citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency
• Candidates will be assessed for the appropriate level during the interview process

About the company

Tenstorrent licenses RISC-V and AI IP to customers. The team has developed a high performance RISC-V CPU from scratch.