AI Silicon, DFT Engineer

The role

As a Member of Technical Staff, DFT Engineer, you will lead the testability realization of a novel computing platform. You will ensure complex digital logic and custom mixed-signal blocks can be reliably tested.

What you will do

• Lead the implementation of comprehensive test architectures using industry-standard CAD tools.
• Drive bottom-up hierarchical DFT methodologies for large-scale SoC designs.
• Own the overarching DFT strategy and work with foundry interfaces to analyze defect densities.
• Drive DFT methodologies for 2.5D/3D multi-stacked die packaging.
• Work at the interface of digital and analog design to facilitate integration and testability of custom analog mixed-signal blocks.
• Drive test coverage, test time, and yield targets while influencing micro-architecture for PPA.
• Own the final DFT sign-off process including ATPG, test vector validation, and fault simulation.
• Contribute to the development and automation of the design flow.
• Evaluate potential partners that offer AI tools to improve chip design efficiency.

Required qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of industry experience in digital DFT and test architecture.
• Track record of successful tapeouts on modern process nodes.
• Deep expertise in scan compression, MBIST generation, fault modeling, and ATPG.
• Deep understanding of physical design challenges in advanced nodes and their impact on test reliability.
• Expertise in Static Timing Analysis (STA) and timing closure for complex designs.
• Expert-level mastery of standard EDA CAD tool suites for DFT implementation and vector generation.
• Strong scripting skills in Tcl, Python, or Perl.
• Excellent written and verbal communication skills.
• Experience managing deliverables from external vendors or design houses.

Nice to have

• Successful tapeouts on 7nm, 5nm, or newer nodes
• Hands-on experience with modern die-to-die (D2D) interconnect test strategies, chiplet testing, and 3D-IC DFT architectures
• Experience with test architecture for Machine Learning accelerators or large-scale systolic arrays
• Experience with top-level integration of large, custom analog macros and complex power-sequencing requirements
• Familiarity with the state of the art AI tools to accelerate chip design

Benefits

• Best-in-class health benefits
• 401k matching
• Truly unlimited PTO
• Complimentary meals in our Mountain View office

About the company

Unconventional is rethinking computing from the ground up to build a new foundation for AI that is 1000x more efficient by exploiting the rich physics of semiconductors.