AI Silicon, Physical Design Engineer

The role

You will lead the physical implementation of complex blocks and top-level SoC integration. This role involves taking digital logic from RTL to GDSII to build a new foundation for AI.

What you will do

• Lead physical implementation of complex blocks and top-level SoC integration.
• Perform floorplanning, power grid design, placement, clock tree synthesis, routing, and physical verification.
• Drive aggressive Power, Performance, and Area (PPA) targets.
• Work with architects to influence micro-architecture for routability and timing closure.
• Own the final sign-off process including STA, IR drop analysis, EM, and Physical Verification.
• Contribute to the development and automation of the physical design flow.
• Set best practices for synthesis, formal verification, and parasitic extraction.
• Work at the interface of digital and analog design to integrate custom analog mixed-signal blocks.
• Evaluate potential partners offering AI tools to improve chip design efficiency.

Required qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of industry experience in digital physical design.
• Track record of successful tapeouts on modern process nodes.
• Expertise in Static Timing Analysis (STA) and timing closure for high-frequency, complex designs.
• Deep understanding of physical design challenges in advanced nodes.
• Proficiency in power integrity analysis and noise coupling mitigation.
• Expert-level mastery of standard EDA tool suites (e.g., Synopsys Fusion Compiler/IC Compiler II or Cadence Innovus).
• Strong scripting skills in Tcl, Python, or Perl.
• Excellent written and verbal communication skills.
• Experience managing deliverables from external vendors or design houses.

Nice to have

• Successful tapeouts on 7nm, 5nm, or newer preferred
• Experience with physical design for Machine Learning accelerators or large-scale systolic arrays
• Experience with top-level integration of large, custom analog macros and complex power-sequencing requirements
• Hands-on experience with multi-voltage domains, UPF/CPF flows, and advanced power-gating techniques
• Familiarity with the state of the art AI tools to accelerate chip design

Benefits

• Best-in-class health benefits
• 401k matching
• Truly unlimited PTO
• Complimentary meals in our Mountain View office

About the company

Unconventional is rethinking computing from the ground up to build a new foundation for AI that is 1000x more efficient by exploiting the rich physics of semiconductors.