Memory Design Engineer

The role

The Memory Design Engineer will work on the architecture, design, compiler development, characterization, and silicon validation of embedded SRAM and Register File IPs for ultra-low-power SoCs. This role involves developing optimized embedded memories operating across conventional, near-threshold, and sub-threshold voltage ranges.

What you will do

• Design ultra-low power embedded SRAM and Register File IPs for advanced SoC products.
• Develop and enhance SRAM compiler architectures supporting multiple memory configurations, banking schemes and redundancy options.
• Design and optimize memory peripheral circuits such as sense amplifiers, write drivers, decoders, word-line drivers, pre-charge circuits, Read/write assist circuits, redundancy and repair logic.
• Optimize memory designs for Area, Performance, Leakage power, Dynamic power, yield and manufacturability.
• Correlate simulation and characterization results with silicon measurements and production test data.
• Analyze low-voltage failure mechanisms including read disturb, write failure, read/write margins, retention failures and process variation effects.
• Drive memory yield improvement through silicon debug, characterization analysis, and design optimization.
• Develop automation scripts using Python, Tcl, or Perl to improve compiler generation, characterization efficiency, regression, and design productivity.
• Collaborate with Memory architecture, Physical design, Timing and STA, DFT/BIST, Product and test engineering, Foundry partners and EDA vendors.
• Support memory IP integration into SoC products from architecture through production release.

Required qualifications

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Electronics, or related discipline.
• Strong understanding of SRAM architecture, compiler design, and custom memory circuit design.
• Proven experience developing embedded SRAM or Register File IP for advanced 12nm FINFET technologies and below.
• Hands-on experience with SRAM compiler development and configurable memory generation.
• Strong expertise in custom memory characterization and production-quality Liberty (.lib) generation.
• Deep knowledge of bit-cell operation, sense amplifier design, read/write assist techniques, low-voltage SRAM operation, process variation analysis, timing and power characterization.
• Experience with Cadence Virtuoso, Spectre, HSPICE or equivalent SPICE simulators, Cadence Liberate MX and Monte Carlo simulations.
• Familiarity with memory compiler architecture and IP delivery flows.
• Experience supporting silicon bring-up, characterization, debug, and production qualification.
• Strong scripting skills in Python, Tcl, Perl, or equivalent programming languages.
• Excellent analytical, debugging, communication, and cross-functional collaboration skills.

Nice to have

• Knowledge of memory redundancy, repair algorithms, ECC, and MBIST integration is highly desirable.

About the company

Ambiq is a provider of ultra-low-power semiconductor solutions based on proprietary sub- and near-threshold technologies. The company has shipped over 260 million units worldwide as of the beginning of 2025.