Sr. Staff Engineer - Digital Design Verification

The role

You will own and execute end-to-end digital verification at block, sub-system, and full-chip levels. This involves developing verification plans and implementing UVM-based testbenches for complex SoCs.

What you will do

• Own and execute end-to-end digital verification at block, sub-system, and full-chip (SoC) levels
• Develop detailed verification plans aligned with architecture and design specifications
• Perform SoC-level verification using full-chip simulation and regression environments
• Architect and implement scalable, reusable UVM-based testbenches using SystemVerilog
• Develop comprehensive test scenarios, stimulus, monitors, and checkers
• Drive constrained-random and directed testing
• Develop and maintain C/C++ based verification libraries and tests for SoC-level validation
• Automate verification flows for regressions, coverage collection, and results reporting
• Define, track, and close functional and code coverage goals
• Utilize advanced debugging methodologies to isolate and resolve complex design and verification issues

Required qualifications

• BSEE or MSEE with 8–12 years of hands-on digital design verification experience
• Proven track record of multiple tape-outs with silicon functioning to specification
• Strong experience in block-level, sub-system, and full-chip SoC verification
• Ability to define and manage verification deliverables, milestones, and schedules
• Proactively identify verification risks and implement mitigation strategies
• Experience working with complex SoCs integrating multiple 3rd-party IPs and VIPs
• Strong collaboration skills to work effectively with design, architecture, and software teams
• Excellent communication skills for reporting status, issues, and progress to stakeholders
• SystemVerilog, UVM, Verilog
• Functional and code coverage methodologies
• Constrained-random verification and scoreboarding
• C/C++ based verification in SoC environments

Nice to have

• Experience with edge-based AI inference workloads
• Experience with processor-based systems (ARM and/or RISC‑V preferred)
• Experience verifying low-power digital architectures and features is highly desirable
• Security IPs (Crypto, OTP)
• DSP and compute-heavy digital subsystems
• High-performance or low-power SoC architectures
• Edge AI / ML workload enablement

About the company

Ambiq is on a mission to enable intelligence everywhere by powering the AI edge revolution with low-power semiconductor solutions. Since 2010, they have shipped over 300 million units to customers building wearables, medical devices, IoT products, and AI-powered edge applications.