Senior/ Staff Formal Verification Engineer

The role

This person will define the formal verification strategy and develop formal verification environments from scratch. They will prove the correctness of complex semiconductor chip designs for AI clusters.

What you will do

• Own and develop formal verification environments from scratch through to sign-off
• Apply formal verification methodologies and strategies to prove the correctness of intricate designs
• Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements
• Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs
• Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently
• Architect and develop generic, common formal functions and properties to be reused across multiple projects

Required qualifications

• Bachelor's degree in Electrical Engineering or a related technical field
• 4+ years of hands-on experience in Formal Verification within semiconductor companies
• Deep expertise in formal verification methodologies, tools, and flows
• Strong understanding of RTL design and verification principles
• Experience with industry-standard formal verification tools (Jasper, VC Formal, or similar)
• Excellent communication skills
• Strong analytical thinking
• Proactive, "can-do" approach to problem-solving

Nice to have

• Track record of successfully taking complex blocks or subsystems through the entire formal verification lifecycle
• Experience with SystemVerilog UVM-based design verification
• Knowledge of networking standards (Ethernet, NVLink, UALink, PCIe)
• Background in high-speed serial interface verification

About the company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.