Staff/ Principal Physical Design STA Engineer

The role

This engineer will execute STA flow and sign-off methodologies for semiconductor chips. You will bridge the gap between Architecture, Design, DFT, and Physical Design to meet timing targets.

What you will do

• Execute the STA flow and sign-off methodologies
• Collaborate with Architecture, Design, DFT, and Backend teams
• Participate in timing reviews and work with block owners for sign-off convergence
• Develop, optimize, and manage complex SDC constraints
• Analyze and resolve challenges related to cross-chip clock distribution networks
• Apply sophisticated margining techniques to ensure robust silicon
• Participate in design methodology improvements and tool automation

Required qualifications

• B.Sc. in Electrical Engineering or Computer Engineering
• 6+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies
• Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels
• Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off
• Solid knowledge of physical design flows (Synthesis, P&R, Physical Verification) and how they intersect with timing closure

Nice to have

• Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia)
• Proven track record of executing STA on complex Macro-level designs and supporting Full-Chip timing integration
• Strong background in scripting (Tcl, Python, Perl) and automation to enhance timing closure efficiency

About the company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company is establishing a strategic R&D center in Israel.