Product Technical Chip Lead, Senior Director

The role

You will drive the end-to-end success of next-generation UALink switching products. You will act as a technical integrator connecting architecture, design, validation, firmware, systems, and operations.

What you will do

• Own the full technical lifecycle of the product line
• Drive chip development execution from RTL to GDSII
• Lead development of large-scale chips utilizing 2.5D/3D advanced packaging and chiplet-based architectures
• Translate product requirements into clear priorities, tradeoffs, and execution paths
• Own the Chip Tapeout and Chip signoff with full responsibility on Chip Quality
• Drive alignment across all engineering functions to resolve risks and dependencies
• Partner with design verification teams to define coverage goals and sign-off criteria
• Collaborate with DFT teams on test architecture and manufacturing test strategies
• Work with physical design teams on timing closure, power optimization, and backend execution
• Establish and reinforce scalable processes, documentation, and handoffs

Required qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 15+ years of experience across architecture, silicon design, validation, systems, or related domains
• Proven track record of developing large-scale chips (300mm²+) through successful tapeout
• Hands-on experience with 2.5D and 3D advanced packaging technologies and chiplet-based architectures
• Strong understanding of RTL design, design verification, DFT, and physical design flows
• Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures
• Demonstrated executive leadership of cross-functional technical programs with end-to-end product cycle ownership
• Strong communication and executive presence with the ability to influence at all levels of the organization

Nice to have

• Master's degree in Electrical Engineering or Computer Engineering
• Experience with UALink, UCIe, PCIe Gen5/Gen6/Gen7, or Ethernet switching architectures
• Experience with advanced process nodes (7nm, 5nm, or below)
• Background in power management, clocking architectures, or high-speed analog integration
• Experience operating in fast-growing startups or hyper-scale environments

Benefits

• discretionary bonus
• incentives
• benefits

About the company

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.