Principal Physical Design Engineer

The role

You will own the backend implementation of complex, high-performance SoCs. You will drive floorplan, timing, power, and signoff decisions for connectivity silicon.

What you will do

• Own the full RTL2GDS flow on advanced process nodes
• Drive block- and chip-level place & route strategy, congestion resolution, and routing convergence
• Architect clock tree synthesis and clocking topology
• Lead tapeout execution including final ECO closure, GDS handoff, and post-tapeout support
• Drive multi-mode multi-corner STA closure, low-power implementation, and IR/EM analysis
• Own physical verification and reliability signoff
• Define methodology for ECO flows, hierarchical timing, and full-chip signoff
• Partner with RTL, DFT, analog/mixed-signal, package, and CAD teams
• Establish and evolve physical design methodology, scripts, and flows
• Mentor engineers, drive design reviews, and represent Physical Design in program-level technical decisions

Required qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 8+ years of physical design experience with multiple tapeouts on advanced process nodes (7nm or below)
• Deep expertise in synthesis, place & route, CTS, and timing closure using industry-standard tools (Synopsys Fusion Compiler / ICC2, Cadence Innovus, PrimeTime)
• Strong command of low-power design techniques (multi-Vt, power gating, DVFS, UPF)
• Proficiency in Tcl/Python scripting for flow automation
• Proven track record delivering high-frequency, high-complexity SoC blocks or full-chip implementations to production

Nice to have

• MS in Electrical Engineering or Computer Engineering
• Experience with high-speed SerDes-heavy designs, PCIe Gen 6/7, or UALink/UCIe-based connectivity SoCs
• Hands-on experience with hierarchical implementation and full-chip integration of large designs (>500M gates)
• Familiarity with EMIR, thermal, and package co-design considerations
• Experience mentoring senior engineers and driving methodology adoption across teams

Benefits

• discretionary bonus
• incentives
• benefits

About the company

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.