Staff Physical Design Engineer - SoC EMIR Engineer

The role

This person will perform SoC EMIR analysis to ensure products meet voltage drop and reliability targets in advanced FinFET process nodes. They will work on IR drop analysis and signal/power electromigration for complex chips.

What you will do

• Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip
• Collaborate closely with Physical Design team to insure a full power integrity
• Partner with Package Design engineers to perform Chip-Package co-analysis (CPM)
• Understand root-cause analysis for voltage drop violations and EM risks

Required qualifications

• Bachelor's or Master's degree in Electrical Engineering or a related technical field
• 7+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products
• Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus)
• Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm)
• Deep understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture
• Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM

Nice to have

• Familiarity with thermal analysis tools and their interaction with electrical performance
• Experience working with sign-off criteria and margins for high-volume production chips
• Good understanding of timing and P&R
• Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution
• Ability to write TCL scripts for STA and Fusion Compiler (FC)

About the company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.