Asteralabs

Soc Design Verification Director

Bengaluru, Karnataka, India. Posted 4 months ago

The role

The Director of SoC Design Verification will lead verification for next-generation System-on-Chip products. This hands-on leadership role involves defining SoC-level verification strategy and overseeing execution across multiple IPs and subsystems.

What you will do

  • Own and drive the end-to-end SoC verification methodology.
  • Lead, mentor, and grow a diverse team of engineers.
  • Guide verification of complex SoC subsystems including HSIO, peripherals, interconnects, memory controllers, coherency fabrics, and system-level protocols.
  • Champion advanced methodologies like UVM, formal verification, emulation, and AI-augmented flows.
  • Collaborate with RTL design, architecture, firmware, and validation teams.
  • Represent verification in executive reviews, customer engagements, and industry forums.
  • Shape workforce transformation by building hybrid skill sets.

Required qualifications

  • Bachelor's degree in Electrical or Computer Engineering
  • 20+ years of experience in design verification
  • Proven track record of leading teams and delivering complex SoC/silicon products
  • Deep expertise in SoC-level verification, including interconnect fabrics, coherency protocols, HSIO, and peripheral subsystems
  • Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design
  • Demonstrated ability to manage priorities, engage with stakeholders, and drive organizational success
  • Hands-on expertise with SoC-level verification environments, including integration of multiple IPs, HSIO, and peripherals
  • Deep experience in UVM-based test plan development, sequence generation, and coverage analysis
  • Strong background in writing assertions, cover properties, and analyzing coverage data at both IP and SoC levels
  • Experience in developing scalable verification infrastructures

Nice to have

  • Master's degree
  • Expertise in verifying complex SoC subsystems such as NoC-based interconnects, coherency fabrics, HSIO, and memory hierarchies
  • Experience with buffering, queuing, QoS, and system-level performance analysis
  • Familiarity with emulation, FPGA prototyping, and hybrid verification flows
  • Knowledge of AI-driven verification methodologies and workforce transformation strategies
  • Experience with AI/ML accelerators, networking, automotive, data center, or high-performance computing SoCs
  • Familiarity with low-power verification methodologies and power-aware verification

Benefits

  • Opportunity to lead cutting-edge SoC development programs
  • Influence verification strategy across next-generation products
  • Build and grow a world-class verification organization
  • Work with highly talented engineering teams on innovative technologies

About the company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.

Soc Design Verification Director at Asteralabs | JobZoey