Senior Principal ASIC Design Engineer

The role

You will drive ASIC design for next-generation Ethernet and Scale-Up connectivity products. You will set technical direction across the full ASIC design flow and lead architecture for high-performance networking components.

What you will do

• Define and drive ASIC architecture for Ethernet/ESUN connectivity products.
• Lead architecture and microarchitecture for Ethernet controllers, MACs, NIC datapaths, and AI interconnect fabrics.
• Define scalable, low-latency, high-bandwidth data movement, scheduling, and congestion management.
• Architect hardware acceleration for NIC functions, RDMA, DMA, virtualization, and protocol offloads.
• Lead tradeoff analysis across performance, power, area, latency, scalability, resiliency, and programmability.
• Lead RTL design and microarchitecture development for networking subsystems.
• Design packet processing architectures, DMA engines, and memory subsystem interfaces.
• Develop hardware mechanisms for RDMA, zero-copy data movement, and transport reliability.
• Design scalable architectures supporting virtualization and traffic management.
• Partner with firmware and software teams to define hardware/software interfaces.

Required qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 12+ years of ASIC/SoC design experience.
• Track record of delivering complex, high-speed networking or connectivity silicon from architecture through production.
• Deep expertise in RTL design and microarchitecture for high-performance networking and connectivity ASICs.
• Extensive experience designing Ethernet controllers, MACs, NIC architectures, packet processing engines, or network interface subsystems.
• Strong understanding of RDMA architectures and transport protocols such as RoCE, InfiniBand concepts, or similar low-latency networking technologies.
• Experience designing hardware for packet parsing, scheduling, buffering, DMA, queue management, flow control, congestion management, and transport acceleration.
• Strong understanding of high-speed interconnects and protocols, including Ethernet, PCIe, and AI scale-up fabrics.
• Hands-on experience across the complete ASIC development flow, including architecture, RTL design, integration, synthesis, timing closure, physical implementation, tapeout, and post-silicon validation
• Demonstrated technical leadership across multiple teams and product programs.

Nice to have

• Master’s or PhD in Electrical Engineering, Computer Engineering, or a related technical discipline.
• Direct experience with UALink, UCIe, PCIe Gen 6/7, and/or advanced Ethernet architectures and protocols.
• Experience designing Ethernet MACs, controllers, SmartNICs, DPUs, NICs, switch datapaths, or packet processing engines.
• Experience developing Ethernet-based scale-up networking solutions for AI and HPC systems.
• Experience leading architecture or design for multiple successful advanced-node ASIC tapeouts.
• Excellent communication, collaboration, and mentorship skills.

About the company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.