Senior Manager, Digital Design

The role

You will lead the front-end digital design of high-performance PCIe, CXL, UAL, and ethernet devices. You will guide projects from requirements and architecture through RTL development, verification, physical design, tape-out, and product shipment.

What you will do

• Lead digital design execution from product requirements and architecture through RTL, verification, tape-out, and production shipment.
• Drive delivery of at least two complex devices, maintaining clear milestones, technical decisions, risk tracking, and schedule accountability.
• Partner with architecture and system teams to translate requirements into robust, scalable digital implementations.
• Set expectations for high-quality front-end RTL for synthesis, timing closure, physical implementation, and tape-out.
• Establish and maintain design checklists, review gates, coding standards, and signoff criteria.
• Resolve design, performance, power, area, clocking, and integration issues with cross-functional teams.
• Lead, mentor, and develop a team of 6–8 digital design engineers.
• Influence cross-functional development decisions and align engineering teams.
• Communicate technical status, tradeoffs, dependencies, and mitigation plans to leadership.

Required qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience with PCIe & CXL, UAL, ethernet digital design, including protocol implementation, high-speed connectivity requirements, and physical-layer considerations.
• 3-5 years of experience in engineering management or technical leadership in digital IC or ASIC design.
• Demonstrated ownership of chip design and development from requirements through tape-out and shipment for at least two devices of reasonable complexity.
• Strong hands-on expertise developing front-end RTL and applying design practices that support predictable physical design progress and tape-out quality.
• Ability to lead 6–8 engineers and influence execution across architecture, verification, physical design, DFT, firmware, validation, and operations.

Nice to have

• Expertise in RTL quality methodologies, design reviews, lint, clock-domain and reset-domain considerations, synthesis, timing, and signoff readiness.
• Experience defining or improving design checklists, development flows, quality gates, and cross-functional tape-out processes.
• Building design blocks with large physical floorplan sizes is a plus
• Track record of balancing performance, power, area, schedule, and risk across large SoC or ASIC programs.
• Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.

Benefits

• discretionary bonus
• incentives
• benefits

About the company

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company’s Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.