Senior Digital Design Engineer

The role

You will design and integrate high-performance connectivity silicon for AI infrastructure. This includes work on architecture, RTL implementation, synthesis, timing closure, and IP integration.

What you will do

• Develop micro-architecture and implement synthesizable RTL for PCIe or Ethernet controllers, bridges, switches, and SerDes-related IP.
• Translate architecture and protocol requirements into scalable designs using SystemVerilog and Verilog.
• Own block-level and full-chip design deliverables from specification through implementation and GDS handoff.
• Integrate controller, SerDes, processor, peripheral, and other IP.
• Drive synthesis, timing analysis, timing closure, clock-domain crossing, lint, and design-quality reviews.
• Support gate-level simulation, emulation, and pre-silicon and post-silicon design implementation activities.
• Contribute to top-level integration, floor-planning discussions, PAD planning, and DFT implementation.
• Collaborate with verification and system teams to assess verification completeness and debug design issues.
• Partner with firmware and embedded software teams to define and validate hardware-software interfaces.
• Use Synopsys and Cadence design and analysis tools, along with Python or Perl scripting.

Required qualifications

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, or a related field.
• 2 - 5 years of experience in digital design and implementation for complex SoC or silicon products.
• Hands-on experience developing RTL in SystemVerilog or Verilog, including synthesis and timing closure.
• Experience with PCIe or Ethernet controller, bridge, switch, PCS, PHY, or SerDes design and IP integration.
• Experience with front-end design, gate-level simulation, clock-domain crossing, lint, or related design-quality methodologies.
• Experience using Python or Perl to automate design, integration, or analysis workflows.
• Ability to collaborate effectively across design, verification, physical design, DFT, firmware, and system teams.
• Authorized to work in Canada.

Nice to have

• Experience with PCIe or Ethernet SerDes controller or IP-level design, including PCIe Gen 6/7, UALink, or UCI.
• Experience with block-level and full-chip implementation at advanced process nodes of 16 nm or smaller.
• Knowledge of PAD design, DFT, floor planning, and top-level integration.
• Experience developing NIC, switch, storage, or other high-performance connectivity products with embedded firmware interaction.
• Familiarity with continuous integration and continuous delivery workflows for design and verification.
• Experience with FPGA-based prototyping, emulation, or post-silicon debug.

Benefits

• Discretionary bonus
• Incentives
• Benefits

About the company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.