Principal PCS/PMA RTL Design Engineer

The role

You will contribute to the architecture, implementation, integration, and verification of PCS/PMA digital logic for high-performance connectivity and networking ASICs. You will translate microarchitectural specifications into synthesizable RTL and collaborate with cross-functional teams to deliver designs through tapeout and silicon validation.

What you will do

• Develop synthesizable Verilog/SystemVerilog RTL for PCS and PMA digital blocks.
• Implement PCS functions like line encoding, scrambling, lane deskew, and rate adaptation.
• Implement forward error correction and related error counters.
• Implement PMA digital interface logic including SerDes datapath interfaces and control interfaces.
• Design lane-level and multi-lane logic including lane bonding and BIST features.
• Translate architectural specifications into datapaths, control logic, and state machines.
• Design reusable, configurable RTL modules.
• Integrate internal and third-party IP.
• Collaborate with design verification engineers to define requirements and test plans.
• Support logic synthesis, timing closure, and power optimization.

Required qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of relevant experience in digital ASIC, SoC, or RTL design, or equivalent academic and industry experience.
• Hands-on experience with Verilog or SystemVerilog RTL development.
• Understanding of digital design fundamentals, including combinational and sequential logic, clocks, resets, state machines, datapaths, FIFOs, and interfaces.
• Working knowledge of at least one high-speed serial protocol (Ethernet, PCIe, UCIe, UALink, CXL, or similar) at the PCS/PHY layer.
• Experience with RTL simulation, debugging, synthesis, and basic timing analysis.
• Familiarity with ASIC design flows and collaboration across design and verification teams.
• Strong communication skills.
• Ability and willingness to work onsite in San Jose, California.

Nice to have

• Master's degree
• Direct experience designing PCS, PMA, or PHY digital logic for Ethernet, PCIe, UCIe, UALink, CXL, or similar standards.
• Experience with PAM4 signaling, FEC, lane deskew/alignment, link training, and equalization control.
• Familiarity with the PIPE specification, 802.3 series, PCIe LTSSM, and UCIe link training and sideband.
• Experience with multi-lane, multi-rate SerDes digital datapaths and clocking architectures.
• Familiarity with interconnect, networking, or data-center ASICs.
• Familiarity with synthesis and implementation tools such as Cadence Genus/Innovus or Synopsys Design Compiler/ICC2.
• Experience with STA using tools such as Synopsys PrimeTime or Cadence Tempus.
• Familiarity with lint, CDC/RDC, DFT, scan, GLS, LEC, UPF, or formal-verification flows.
• Experience with UVM, SystemVerilog Assertions, functional coverage, or verification-plan development.

Benefits

• Discretionary bonus
• Incentives
• Benefits

About the company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.