Principal Logic Design Engineer - UALink IP/Subsystem

The role

This person will lead RTL and microarchitecture development for UALink-based IP/subsystems. They will design high-bandwidth, low-latency data paths and control logic.

What you will do

• Lead architecture and RTL development for UALink IP/subsystems.
• Translate protocol and system requirements into scalable hardware architecture.
• Design high-bandwidth, low-latency data paths and control logic.
• Develop mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.
• Define interfaces between UALink and other SoC/interconnect components.
• Develop and review SystemVerilog RTL.
• Drive design optimization for performance, power, area, and latency.
• Work closely with verification, physical design, SoC integration, and firmware teams.
• Review design specifications and contribute to architectural decisions.
• Debug complex simulation and integration issues.

Required qualifications

• 10–15 years experience
• Strong experience in RTL and microarchitecture development.
• Experience with high-speed interconnects and/or coherent fabrics.
• Strong understanding of computer architecture, networking/interconnect concepts, and data movement.
• Proficiency in SystemVerilog/Verilog.
• Strong understanding of CDC, reset architecture, performance, and hardware design methodology.

Nice to have

• Direct UALink experience.
• Experience with PCIe, CXL, CCIX, CHI, Ethernet, or similar protocols.
• Experience in AI/accelerator or high-performance compute systems.

About the company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.