Asteralabs

Teach Lead Physical Design Engineer

Singapore, Singapore. Posted a month ago

The role

This person will perform block-level and top-level physical implementation for next-generation transceiver IPs. They will work on advanced technology nodes including TSMC 3nm.

What you will do

  • Perform block-level and top-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification.
  • Collaborate with RTL and STA teams to ensure clean handoffs and support timing, area, and power convergence.
  • Apply advanced physical design techniques to support multiple voltage and frequency domains, hierarchical design, and physical-aware synthesis.
  • Perform EM/IR analysis and power grid optimization.
  • Perform congestion analysis and mitigation.
  • Perform clock skew optimization and clock quality improvement.
  • Perform RC extraction-aware placement and routing.
  • Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment.
  • Support floorplan development and chip partitioning for high-speed transceiver designs.
  • Perform ECO implementation and assist with tapeout signoff activities.

Required qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
  • 5+ years of experience in physical design.
  • Experience with floorplanning, placement, CTS, routing, and IR drop mitigation.
  • Experience with signoff checks such as DRC, LVS, ANT, and ERC, along with debugging.
  • Experience with timing closure support in collaboration with STA teams.
  • Hands-on use of tools such as Synopsys ICC2, Cadence Innovus, Calibre, and Voltus.
  • Experience integrating high-speed IPs such as SerDes or PHYs into SoC or chiplet-based environments.
  • Experience working on high-frequency datapath and DSP-related designs.
  • Solid scripting skills for automation and productivity enhancement.
  • Good problem-solving skills and the ability to work effectively in cross-functional teams.

Nice to have

  • experience with advanced technology nodes

About the company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.

Teach Lead Physical Design Engineer at Asteralabs | JobZoey