Senior Analog Mixed-Signal IC Layout Engineer

The role

The Analog / Mixed-Signal Layout Engineer will join the ASIC team to work on high-performance compute and networking standards in advanced CMOS process nodes. You will be responsible for design and/or verification of blocks using leading edge methodology and tools.

What you will do

• Design and/or verification of blocks using leading edge methodology and tools

Required qualifications

• Pursuing BS or MS in EE/CS or related fields
• Hardware engineering background with an emphasis in VLSI or Computer Architecture
• Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture
• Hands-on and knowledge of RTL design languages and tools including Verilog, System Verilog
• Familiarity with verification methodologies like UVM, functional coverage, assertions
• Familiarity with any of the scripting languages Python, Perl etc
• Hands-on experience in C/C++

Nice to have

• Real-world design and/or verification in Verilog/System Verilog
• Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes
• Familiarity with Synopsys EDA tools
• Exposure to high-speed interfaces PCIE, DDR, HBM, Serdes technologies

About the company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.