Senior Design Verification Engineer

The role

You will define and deliver verification for next-generation connectivity silicon. You will build verification strategies, develop UVM-based testbenches, and drive coverage closure for PCIe and UALink connectivity products.

What you will do

• Develop block- and subsystem-level verification plans from specifications, architecture, and design requirements.
• Define test scenarios, coverage models, checkers, assertions, and scoreboards.
• Review designs and verification plans with architecture and RTL teams.
• Build and enhance reusable UVM-based SystemVerilog testbenches, agents, sequences, monitors, and reference models.
• Create directed, constrained-random, and power-on-reset scenarios.
• Debug simulation failures using waveform analysis, logs, assertions, and cross-functional collaboration.
• Drive functional and code coverage analysis and close coverage to milestones.
• Develop regression strategies and automation.
• Partner with design and post-silicon teams on issue isolation, root-cause analysis, and silicon bring-up readiness.

Required qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 2–5 years of experience in design verification for complex ASICs or SoCs.
• Hands-on experience with SystemVerilog and UVM-based verification environments.
• Experience developing verification plans, testbenches, assertions, scoreboards, and functional coverage models.
• Familiarity with simulation, waveform-debug, regression, and coverage tools.
• Strong debugging, communication, and collaboration skills.

Nice to have

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience verifying PCIe, UALink, UCI, or other high-speed connectivity and switching protocols.
• Knowledge of protocol checkers, formal verification, emulation, or hardware acceleration methodologies.
• Experience with Python, Perl, or Tcl for verification automation and regression infrastructure.
• Understanding of AI or data-center system architectures, including accelerator, memory, and fabric connectivity.

Benefits

• discretionary bonus
• incentives
• benefits

About the company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.