Principal Physical Design Engineer

The role

The Principal Physical Design Engineer will drive multiple complex designs from architecture to GDSII. This role involves full chip or block level ownership for SoC/silicon products.

What you will do

• Drive multiple complex designs to production
• Full chip or block level ownership from architecture to GDSII
• Work with IP vendors for both RTL and hard-mac blocks

Required qualifications

• Bachelor's degree in EE / Computer
• 8 or more years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications
• Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less
• Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level
• Experience with Cadence and/or Synopsys physical design tools/flows
• Familiarity and working knowledge of System Verilog/Verilog
• Experience with DFT tools and techniques
• Experience in working with IP vendors for both RTL and hard-mac blocks
• Good scripting skills in python or Perl

Nice to have

• Master's degree
• 7nm or less technology experience
• Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
• Familiarity with DFT test coverage and debug
• Familiarity with ECO methodologies and tools

About the company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.